Effect of gate oxide thickness on polycrystalline silicon thin-filmtransistors

Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/9011

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DC Field	Value	Language
dc.contributor.author	Gupta, Navneet	-
dc.date.accessioned	2023-02-06T11:02:43Z	-
dc.date.available	2023-02-06T11:02:43Z	-
dc.date.issued	2007	-
dc.identifier.uri	https://www.tsijournals.com/articles/effect-of-gate-oxide-thickness-on-polycrystalline-silicon-thinfilmtransistors.pdf	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9011	-
dc.description.abstract	This work presents the study of the effect of gate oxide thickness on the performance of lightly doped polycrystalline silicon thin-filmtransistors with large grains. It is observed that scaling down of the oxide thickness is an efficient way to reduce the threshold voltage and hence to improve the poly- Si TFT characteristics. A reasonably good fitting between the analytical results and the experimental data support the validity of this model.	en_US
dc.language.iso	en	en_US
dc.publisher	Trade Science Inc	en_US
dc.subject	EEE	en_US
dc.subject	Polysilicon	en_US
dc.subject	Gate oxide	en_US
dc.subject	Threshold voltage	en_US
dc.subject	TFTs.	en_US
dc.title	Effect of gate oxide thickness on polycrystalline silicon thin-filmtransistors	en_US
dc.type	Article	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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