Please use this identifier to cite or link to this item:
                
    
    http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/9011| Title: | Effect of gate oxide thickness on polycrystalline silicon thin-filmtransistors | 
| Authors: | Gupta, Navneet | 
| Keywords: | EEE Polysilicon Gate oxide Threshold voltage TFTs.  | 
| Issue Date: | 2007 | 
| Publisher: | Trade Science Inc | 
| Abstract: | This work presents the study of the effect of gate oxide thickness on the performance of lightly doped polycrystalline silicon thin-filmtransistors with large grains. It is observed that scaling down of the oxide thickness is an efficient way to reduce the threshold voltage and hence to improve the poly- Si TFT characteristics. A reasonably good fitting between the analytical results and the experimental data support the validity of this model. | 
| URI: | https://www.tsijournals.com/articles/effect-of-gate-oxide-thickness-on-polycrystalline-silicon-thinfilmtransistors.pdf http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9011  | 
| Appears in Collections: | Department of Electrical and Electronics Engineering | 
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.