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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chaubey, V.K. | - |
dc.contributor.author | Shekhar, Chandra | - |
dc.date.accessioned | 2023-02-07T04:18:51Z | - |
dc.date.available | 2023-02-07T04:18:51Z | - |
dc.date.issued | 2019-05 | - |
dc.identifier.uri | https://link.springer.com/article/10.1007/s11277-019-06549-x | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9024 | - |
dc.description.abstract | This paper presents a new algorithm to construct a XOR-Free architecture of an area efficient Walsh generator. The approach completely removes the modulo-two operations required for extracting zero crossing and parity in the generation. In its place a new Transition Sequence based approach is introduced to obtain that string. The string then, becomes input to a triggered flip-flop and generate 2n Walsh sequences in dyadic ordering. The approach reduces the conventional sequential design to semi-sequential and thereby reduces the encoding/decoding cost with lesser design complexity. Results of the proposed architecture reduces the area up to 25–90% by extracting both the symmetry and state isomorphism. Further, it improves dynamic power consumption up to 3–60% with increasing sequence length as compare to conventional approach. The hardware co-simulation of the architecture is first validated and then implemented with Xilinx ZYNQ FPGA. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Springer | en_US |
dc.subject | EEE | en_US |
dc.subject | XOR-Free architecture | en_US |
dc.subject | Xilinx ZYNQ FPGA | en_US |
dc.title | A New XOR-FREE Approach to Implement Walsh Sequences | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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