Transition sequence based Walsh Encoder: A novel power efficient architecture

Abstract

This paper presents a new algorithmic approach to construct a generic Nth Order Walsh Functions (WF) using Transition Sequence (TS). The TS acts as a pointer to the desired Walsh Index (WI) and produces the Sign Change string (S). This string becomes input to a triggered flip flop to generate 2n Walsh Sequences (WS). The proposed strategy totally removes the obvious use of modulo 2 adders leading to a simpler Isomorphic architecture. The FPGA implementation of the generated WS shows a superior performance for higher order WF (n) up to 9. This novel approach reduces Hardware (HW) area by 25–90% and Dynamic Power (DP) by 3–60%, with varying n from 4 to 9, as compared to pure sequential design approach. The proposed design has been tested and verified on the Xilinx Virtex-5 platform.