Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/9031
Title: | XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware |
Authors: | Chaubey, V.K. |
Keywords: | EEE Algorithm Lookup Table (LUT) |
Issue Date: | 2016 |
Publisher: | ACM Digital Library |
Abstract: | This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW) implementation of new architecture uses Lookup Table (LUT) for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA. |
URI: | https://dl.acm.org/doi/abs/10.1155/2016/9128683 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9031 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.