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Title: | A New XOR-Free Approach for Implementation of Convolutional Encoder |
Authors: | Chaubey, V.K. |
Keywords: | EEE XOR-Free architecture Read-only memory (ROM) Xilinx Virtex-V FPGA Architecture |
Issue Date: | Mar-2016 |
Publisher: | IEEE |
Abstract: | This letter presents a new algorithm to construct an XOR-Free architecture of a power efficient Convolutional Encoder. Optimization of XOR operators is the main concern while implementing polynomials over GF(2), which consumes a significant amount of dynamic power. The proposed approach completely removes the XOR-processing operation of a chosen nonsystematic, feed-forward generator polynomial and reduces the logical operators, thereby the encoding cost. Hardware (HW) implementation of the proposed design uses Read-only memory (ROM) with a preprocessed addressing operations to reduce ROM size by nearly 50%. The results of the new architecture reduce the dynamic power up to 21.4% and HW cost up to 15% with lesser design complexity as compared to conventional method. The Hardware cosimulation of the architecture is first validated and then implemented with Xilinx Virtex-V FPGA. |
URI: | https://ieeexplore.ieee.org/document/7323829 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9033 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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