DSpace logo

Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/9084
Full metadata record
DC FieldValueLanguage
dc.contributor.authorChaubey, V.K.-
dc.date.accessioned2023-02-08T09:17:09Z-
dc.date.available2023-02-08T09:17:09Z-
dc.date.issued2011-
dc.identifier.urihttps://ieeexplore.ieee.org/document/6139451-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9084-
dc.description.abstractOne of the key problems in application of packet switching in optical domain is the handling of packet contentions that take place when two or more incoming packets are directed to the same output line. This problem can be solved by incorporating fiber delay lines (FDLs) in the switch architecture. In the present paper simulated behavior of an optical node has been realized by using an n × m optical switch and recirculating optical delay lines, A mathematical model for the proposed switch architecture is developed employing packet queuing control to estimate the blocking probability for the incoming traffic. This investigation infers the scaling behaviors of the proposed architecture to maintain efficient use of the buffer under Poisson traffic loading.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectOptical Packet Switching Networksen_US
dc.subjectFiber Delay Linesen_US
dc.subjectPacket Recirculationen_US
dc.subjectContention Resolutionen_US
dc.subjectNode architectureen_US
dc.subjectIncoming Trafficen_US
dc.subjectThroughputen_US
dc.titleModeling and performance analysis of optical packet switching network using fiber delay linesen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.