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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Gupta, Anu | |
dc.contributor.author | Asati, Abhijit | |
dc.date.accessioned | 2023-02-09T09:28:23Z | |
dc.date.available | 2023-02-09T09:28:23Z | |
dc.date.issued | 2018 | |
dc.identifier.uri | https://www.tandfonline.com/doi/full/10.1080/00207217.2018.1440437 | |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9108 | |
dc.description.abstract | In scaled technologies with lower supply voltage, conventional Static Random Access Memory (SRAM) cell suffers from unsuccessful read & write operation due to high off state current in sub-threshold region at nanometre technologies. This work proposes new functional low-power designs of SRAM cells with 7, 8, 9 and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. Stability analysis is carried out using static noise margins as well as N-curve cell stability metrics. For performance measurement, read/write access time and leakage power consumption in hold mode are analysed. The comparison with published designs shows that two new proposed designs namely M8T, MPT8T have 30% less leakage power consumption along with 2× read stability, 2× write ability, more than 60% faster read & write operation. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Taylor & Francis | en_US |
dc.subject | SRAM | en_US |
dc.subject | EEE | en_US |
dc.subject | Low power | en_US |
dc.subject | Sub-threshold | en_US |
dc.subject | Static noise margin | en_US |
dc.subject | Variability | en_US |
dc.title | Novel low-power and stable SRAM cells for sub-threshold operation at 45 nm | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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