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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/9110
Title: Hardware Accelerators for Iris Localization
Authors: Gupta, Anu
Asati, Abhijit
Keywords: EEE
Field programmable logic array (FPGA)
Circular Hough Transform (CHT)
Issue Date: Sep-2017
Publisher: Springer
Abstract: This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work.
URI: https://link.springer.com/article/10.1007/s11265-017-1282-2
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9110
Appears in Collections:Department of Electrical and Electronics Engineering

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