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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/9110
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dc.contributor.authorGupta, Anu
dc.contributor.authorAsati, Abhijit
dc.date.accessioned2023-02-09T09:34:25Z
dc.date.available2023-02-09T09:34:25Z
dc.date.issued2017-09
dc.identifier.urihttps://link.springer.com/article/10.1007/s11265-017-1282-2
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9110
dc.description.abstractThis paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work.en_US
dc.language.isoenen_US
dc.publisherSpringeren_US
dc.subjectEEEen_US
dc.subjectField programmable logic array (FPGA)en_US
dc.subjectCircular Hough Transform (CHT)en_US
dc.titleHardware Accelerators for Iris Localizationen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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