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Title: | Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology |
Authors: | Gupta, Anu |
Keywords: | EEE C-CMOS Carbon nanotube (CNT) field effect transistor (CNTFET) Ternary logic Ternary ALU (TALU) Power-delay product (PDP) |
Issue Date: | Apr-2015 |
Publisher: | Taylor & Francis |
Abstract: | This paper proposes a hardware-efficient low-power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor technology. The proposed TALU architecture combines adder-subtractor and Ex-OR cell in one cell, thereby reducing the number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimised at transistor level with a new pass-transistor logic-based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively. |
URI: | https://www.tandfonline.com/doi/full/10.1080/00207217.2015.1082199 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9115 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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