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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/9130
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dc.contributor.authorGupta, Anu-
dc.date.accessioned2023-02-10T03:57:53Z-
dc.date.available2023-02-10T03:57:53Z-
dc.date.issued2009-
dc.identifier.urihttps://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=e4053b042b25ed657dd7fb62aa7d8aae7b313cdc-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9130-
dc.description.abstractThis paper proposes an approach for designing a R-2R 10 bit Digital to Analog Converter (DAC) which could be made to operate at low voltage supply by efficiently exploiting the cascaded Operational Amplifier (Op-Amp) architecture. The DAC operates at a 3V power supply with a settling time of 50-100ns , dynamic range of around 50-60 dB for signals upto a frequency of 10Mhz. Graph & simulation results are provided to verify the stability of the Op-Amp used in DACen_US
dc.language.isoenen_US
dc.publisherACEEEen_US
dc.subjectEEEen_US
dc.subjectCascaded Op-Amp Topologyen_US
dc.subjectDACen_US
dc.subjectDigital to Analog Converteren_US
dc.titleDesign of 10-bit Digital to Analog Converter Using Cascaded Operational Amplifier Topologyen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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