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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/9147
Title: Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology
Authors: Gupta, Anu
Keywords: EEE
CMOS Circuit
Issue Date: 2012
Publisher: CEEE
Abstract: The Logical Effort model is mainly to reduce delay in a circuit, but does not show how to minimize power and area. This paper deals with an empirical modeling and design of logical effort for estimating power in CMOS logic gates. The power is estimated in a circuit using the power of standard inverter and the relationship established between Power (P) and Logical Effort (g), Electrical Effort (h) and Parasitic (p) have been proposed in this paper. To verify the above model a full adder circuitry producing just the carry-out in UMC 90nm CMOS technology having supply voltage of 1V is selected. The results obtained from the model are accurate to 85.5% of the values obtained. The tool used is cadence and the simulation is performed using spectrum
URI: https://www.seekdl.org/conferences/get/paper/46.html
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9147
Appears in Collections:Department of Electrical and Electronics Engineering

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