Characterization of Logical Effort for Improved Delay

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DC Field	Value	Language
dc.contributor.author	Gupta, Anu	-
dc.date.accessioned	2023-02-10T09:51:31Z	-
dc.date.available	2023-02-10T09:51:31Z	-
dc.date.issued	2013	-
dc.identifier.uri	https://link.springer.com/chapter/10.1007/978-3-642-42024-5_14	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9149	-
dc.description.abstract	In this paper, an effort has been made to improve the delay of a gate by skewing the gates by choosing proper sizing. The expression for skewed logical effort has been derived for universal logic gates namely NOT, NAND and NOR for minimizing the delay. The validations for minimum delay through simulation was done on a chain of inverters. The improved skewed gates showed 10% - 20% delay reduction on a chain of inverters as compared with normal skewed gate, high and low skewed gates, whereas, an improvement of 20% - 25% when compared to skewed gates favoring a particular transition. All simulations are done using Spectre in Cadence environment in UMC90nm CMOS technology at 1V power supply.	en_US
dc.language.iso	en	en_US
dc.publisher	Springer	en_US
dc.subject	EEE	en_US
dc.subject	Characterization	en_US
dc.subject	CMOS technology	en_US
dc.subject	Delay	en_US
dc.subject	Logical effort	en_US
dc.subject	Skewed gate	en_US
dc.title	Characterization of Logical Effort for Improved Delay	en_US
dc.type	Article	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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