DSpace logo

Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/9156
Full metadata record
DC FieldValueLanguage
dc.contributor.authorGupta, Anu-
dc.date.accessioned2023-02-10T10:15:51Z-
dc.date.available2023-02-10T10:15:51Z-
dc.date.issued2013-
dc.identifier.urihttps://ieeexplore.ieee.org/document/6731187?reload=true-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9156-
dc.description.abstractA frequency compensation technique for achieving high 3-dB bandwidth in two-stage operational amplifiers is demonstrated in this paper. Due to the phenomenon of pole splitting in Miller's Compensation technique in classical op-amp, the 3-dB bandwidth reduces drastically. The technique demonstrated in this paper is a modification of Miller's Compensation technique to achieve a significant improvement in the 3-dB bandwidth by introducing an extra stage, consisting of MOS transistors (MOST). The coupling capacitor and a PMOS transistor operating in triode region is connected between the output of the extra stage and the input of the second stage. The simulations were carried out in Cadence VIRTUOSO environment using 0.18 μm CMOS process technology.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subject3-dB Bandwidthen_US
dc.subjectPhase Marginen_US
dc.subjectTwo-Stage Operational Amplifieren_US
dc.subjectCoupling Capacitoren_US
dc.subjectFrequency Compensationen_US
dc.titleFrequency compensation in two-stage operational amplifiers for achieving high 3-dB bandwidthen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.