An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style

Abstract

The Array multipliers are generally preferred for smaller operand sizes due to their simpler VLSI implementations, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are unsuitable for VLSI implementation since they require larger total routing length, which may degrade performance. The properties of simpler VLSI implementation can be combined with fully pipelined circuit design using CMOS TSPC (true single phase clock) logic design style to improve throughput of array multipliers. In this paper an improved high speed, fully pipelined 8times8 signed Baugh Wooley multiplier circuit has been designed and implemented using CMOS TSPC logic in 0.6 mum, N-well CMOS process (SCN_SUBM, lambda=0.3) of MOSIS utilizing optimized TSPC logic cells. The simulation results after parasitic extraction show that the inputs can be applied every clock and it can produce correct output after 17 clock cycles at 500 MHz clock rate. Thus the throughput of 500times10 6 multiplication per second is achieved using TSPC based fine grain pipelining. By designing and using novel TSPC full adder cell, our Baugh Wooley multiplier implementation shows large reduction in transistor count, average power and delay as compared to an implementation by Robert Rogenmoser and Qiuting Huang. The total transistor count, average power and maximum instantaneous power are indicated in comparison table