Scheduling of dataflow graphs on partial reconfigurable hardware in Xilinx PR flow

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DC Field	Value	Language
dc.contributor.author	Asati, Abhijit	-
dc.date.accessioned	2023-03-02T05:39:47Z	-
dc.date.available	2023-03-02T05:39:47Z	-
dc.date.issued	2013	-
dc.identifier.uri	https://ieeexplore.ieee.org/abstract/document/6659371	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9417	-
dc.description.abstract	Partitioning and scheduling of dataflow graphs(DFGs) has been a matter of extensive research for ASIC based development. With the advent of partial reconfigurable hardware the need to schedule DFGs with restricted resources is required. In this research we test and extend the conventional scheduling algorithm suited for reconfiguration. In algorithm we restrict the flow as offered by Xilinx in PR design. The performance of such flow should be much significant than the conventional software execution flow. Hence we estimate the timing comparison of the software and the hardware flow	en_US
dc.language.iso	en	en_US
dc.publisher	IEEE	en_US
dc.subject	EEE	en_US
dc.subject	Partitioning and Scheduling(PaSc)	en_US
dc.subject	Partial reconfiguration	en_US
dc.subject	DFGs	en_US
dc.subject	Xilinx	en_US
dc.title	Scheduling of dataflow graphs on partial reconfigurable hardware in Xilinx PR flow	en_US
dc.type	Article	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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