A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Logic Design Style With Improved Performance

Abstract

The high-speed dynamic True Single Phase Clock (TSPC) logic design style offer fully pipelined logic circuits using only one clock signal, which makes clock distribution simple and compact. The conversion of simple logic gates to pipelined TSPC logic gates increases transistor count since standard cell implementation for a logic function uses both N-block as well as P-block to remove transparency between pipelined stages, despite the fact that logic functions are only implemented with N-block. In this paper we present a technique in which a TSPC logic cell are implemented both as cell_N and cell_P cells, where each cell block is performing a logic function along with only one type latching operation. Such an implementation allows a systematic approach for converting un-pipelined circuits to fully pipelined circuits. The alternate cell_N and cell_P behaves as dynamic register and removes transparency between pipelined stages. The appropriate numbers of dynamic registers are used to equalize stage delays for all paths and to remove transparency between pipelined stages. The modified TSPC implementation shows almost 40% to 50% reduction in transistor counts and almost 50% reduction in clock cycles as compared to worst-case standard TSPC implementation. The worst-case standard TSPC implementation assumes that no logic merging is possible with P-block, since input to any cell appears after different cycle delays. The modified TSPC logic circuit implementation preserves all the advantages of standard TSPC logic implementation and in addition offers the reduced circuit complexity due to reduced transistor count per logic cell. The proposed logic design style reduces layout area and average power consumption as compared to the standard TSPC pipelined circuit implementation