Automated HDL generation of two’s complement Dadda multiplier with Parallel Prefix Adders

Abstract

Dadda multipliers are among the fastest multipliers owing to their logarithmic delay. The partial products of two‟s complement multiplication are generated by an algorithm described by Baugh-Wooley. The complicated and irregular reduction of partial products by Dadda algorithm and use of Parallel Prefix adders with logarithmic delay in the final stage of addition makes it difficult to write a generic Verilog code for them. To solve this difficulty, we described a C program which automatically generates a Verilog file for a Dadda multiplier with Parallel Prefix adders like Kogge-Stone adder, Brent-Kung adder and Han-Carlson adder of user defined size. We compared their post layout results which include propagation delay, area and power consumption. The Verilog codes have been synthesized using 90 nm technology library. We observed that the multiplier using Kogge-Stone adder in the final stage gives higher speed and lower Power Delay Products when compared to that using Brent-Kung and Han-Carlson adders