Analysis of Logical Effort-Based Optimization in the Deep Submicron Technologies

Abstract

A convenient way to estimate and optimize the delay of VLSI digital circuits is the popular logical effort-based optimization. In this paper, we analyzed the effect of various circuit parameters such as logical effort (G), branching effort (B), electrical effort (H), and parasitic effort (P) on the delay of a given circuit for two different technology nodes, namely 180 and 16 nm. The analysis results show the variation of delay with a particular logical effort parameter. The variation between simulation delay and logical effort delay is indicated by a parameter τ’, which is compared with the τ which is the delay of an inverter driving an identical inverter with no parasitic for a chosen technology. The effectiveness of the logical effort-based optimization is explored. Further, the logical effort-based delay reduction, a super buffer-based delay reduction, and delay of an un-optimized circuit are also compared. The effect of technology on logical effort method for each parameter in the deep submicron sizes has also been investigated in this research work.