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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/9436
Title: Dedicated hardware architecture for localizing iris in VW images
Authors: Asati, Abhijit
Gupta, Anu
Keywords: EEE
Dedicated hardware architecture
FPGA based implementation
Iris localization
Issue Date: Jul-2022
Publisher: Elsevier
Abstract: This study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems. Though the hardware architecture is described for iris localization in the visible wavelength (VW) images, the concept used can be applied to near infrared (NIR) images as well. In general, the architecture can be used for a class of iris localization algorithms based on the edge-map generation and circular Hough transform (CHT). The architecture presented here generates the edge-maps for limbic and pupil boundary detection using median filtering followed by Sobel edge detection; however, an additional reflection removal module is used for pupil boundary detection. Further, the CHT hardware module detects circle in each edge-map. The proposed architecture was implemented in programmable logic of the Zynq-7000 SoC device from Xilinx. This hardware implementation gives an iris localization accuracy of 98.43% and average processing time of 5.148 ms for UBIRIS.v1 VW database images (200 × 150 pixel). The algorithm used is suitable for less unconstrained and frontal-view iris images captured with subjects’ active participation; however, the images may contain non-ideal issues such as reflection and occlusion by eyelids and eyelashes.
URI: https://www.sciencedirect.com/science/article/pii/S1319157820305292
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9436
Appears in Collections:Department of Electrical and Electronics Engineering

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