Adiabatic Logic Code Converter Design at Different Sub-micron Technologies

Abstract

In modern VLSI design, the focus is shifting toward low-power VLSI design techniques to reduce the power density on the chip. Adiabatic logic is suitable in design of low-power VLSI circuits. In this work, we focus on design and analysis of digital code converters. The code converters designed in this work are, namely, gray to binary, binary to gray, and BCD to excess-3 using different logic styles of adiabatic logic at different technology nodes. The adiabatic styles used for design of the code converters in this work are ECRL, IPGL, and 2N_2N2P, and for comparison of power and PDP metrics, static CMOS implementation is taken as reference. All simulations are performed using LTspice simulator at 32, 22, and 16 nanometer technology nodes using PTM models. We have also compared various metrics such as delay, power, and power–delay product (PDP) metrics of the circuits using different logic styles and at different technology nodes.