Low-Area, High-Throughput Field-Programmable Gate Array Implementation of Microprocessor Without Interlocked Pipeline Stages

Abstract

Microprocessors without interlocked stages (MIPS) are based on the reduced instruction set computer architecture. These processors have been in use for years and remain in wide use today in applications such as automation, processing, and communication. Many of these applications must be run on smaller, low-cost target boards with limited resources. Field-programmable gate arrays (FPGAs) are also gaining importance in the very large scale integration design flows because their parallel architecture makes them very fast. Some low-cost FPGAs also offer limited on chip resources such as lookup tables and flip flops. Furthermore, high-level synthesis is gaining popularity among designers because it offers a higher level of design abstraction along with continued verification during the design flow. In this paper, we propose a low-area MIPS processor with high throughput. We use high-level synthesis to generate register transfer level code for the 32-bit MIPS core and target the same for Virtex 7 FPGA. We optimize the design for area and performance using selected high-level synthesis directives, which produces results superior to those reported in the literature.