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Title: | Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load |
Authors: | Asati, Abhijit Shekhar, Chandra |
Keywords: | EEE Inverters MOS devices CMOS logic circuits Logic design Logic devices Logic gates Circuit noise CMOS technology |
Issue Date: | 2009 |
Publisher: | IEEE |
Abstract: | The PMOS/NMOS width ratio (ß) and W/L ratio of NMOS device is an important ratio in the design of digital logic cells using conventional CMOS logic design style. In this paper we propose a simulation-based method applied to CMOS inverter to accurately estimate an optimum W/L ratio of NMOS device and PMOS/NMOS width ratio when fanout loading of 1, 4 and 8 cells of similar type are present. The appropriate selection of W/L ratio of NMOS device and PMOS/NMOS width ratio makes the digital design faster and reduces the power consumption. |
URI: | https://ieeexplore.ieee.org/abstract/document/5395495 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9459 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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