Logic Design Style based NBTI Degradation Study using Verilog

Abstract

Negative Bias Temperature Instability (NBTI) is identified as one of the most critical reliability concerns for nanometer scale digital VLSI integrated circuits. Degradation occurring in threshold voltages of PMOS device is most critical as it decides the lifetime of digital circuits in the deep sub-micron technologies. Research on NBTI is active only within community of the device and reliability physics and leading industrial companies develop their models and tools to handle this effect. In this paper we used a switch level Verilog HDL based circuit modeling which incorporates dynamically growth of NBTI effect in transistor switches and its evolutionary impact on circuit performance with time. The proposed technique of NBTI degradation estimation shows dependence of Vt degradation on the minimum period of applied input vectors when input vectors follow temporal randomness which is ignored in the existing techniques. The circuit model was prepared for a 2-input AND gate designed using four different CMOS logic design styles namely static, transmission gate (TG), domino and true single phase clock (TSPC). The AND gate is described using switch level Verilog code incorporates the model for computing the change in threshold voltage (dVt) of PMOS devices after every NBTI stress phase and recovery phase. NBTI stress can be computed by knowing the time for which particular PMOS remain under negative bias (i.e. Vgs<0). In this study, a set of temporal random input vectors corresponding to 0.5-5 year (changing every 5 second) is applied to the AND gate for all four logic design styles to observe the effect of NBTI degradation i.e. the worst threshold voltage degradation of the all PMOS devices in a AND gate at 50o C and 100o C. The comparison shows that AND gates designed using TSPC and domino shows larger worst case degradation in Vt as compared to the static and TG logic design style.