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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/9719
Title: An efficient adaptive block pinning for multicore architectures
Authors: Chaturvedi, Nitin
Keywords: EEE
Processor Owned Private (POP) cache
Chip Multiprocessors (CMP)
Compulsory miss
Conflict miss
Capacity miss
Issue Date: May-2015
Publisher: Elsevier
Abstract: Most of today’s multi-core processors feature last level shared L2 caches. A major problem faced by such multi-core architectures is cache contention, where multiple cores compete for usage of the single shared L2 cache. Previous research shows that uncontrolled sharing leads to scenarios where one core evicts useful L2 cache content belonging to another core. To address this problem, the paper first presents a cache miss classification scheme – CII: Compulsory, Inter-processor and Intra-processor misses – for CMPs with shared caches and its comparison to the 3C miss classification for a traditional uniprocessor, to provide a better understanding of the interactions between memory references of different processors at the level of shared cache in a CMP. We then propose a novel approach, called block pinning for eliminating inter-processor misses and reducing intra-processor misses in a shared cache. Furthermore, we show that an adaptive block pinning scheme improves over the benefits obtained by the block pinning and set pinning scheme by significantly reducing the number of off-chip accesses. This work also proposes two different schemes of relinquishing the ownership of a block to avoid domination of ownership by a few active cores in the multi-core system which results in performance degradation. Extensive analysis of these approaches with SPEC and PARSEC benchmarks are performed using a full system simulator.
URI: https://www.sciencedirect.com/science/article/pii/S0141933115000162
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9719
Appears in Collections:Department of Electrical and Electronics Engineering

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