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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chaturvedi, Nitin | - |
dc.date.accessioned | 2023-03-14T11:02:27Z | - |
dc.date.available | 2023-03-14T11:02:27Z | - |
dc.date.issued | 2015 | - |
dc.identifier.uri | https://www.sciencedirect.com/science/article/pii/S187705091500023X | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9722 | - |
dc.description.abstract | In current multi-core systems with the shared last level cache (LLC) physically distributed across all the cores, both initial data placement and subsequent placement of data close to the requesting core can contribute to reducing memory access latency and power consumption. This paper extends a replication scheme that balances between access latency and cache capacity in shared NUCA designs by selectively replicating frequently used cache lines close to the requesting cores. Our scheme reduces completion time by 15% and improves energy consumption by 27% when compared to the Static-NUCA (S-NUCA) management scheme, when simulated on an eight core system. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Elsevier | en_US |
dc.subject | EEE | en_US |
dc.subject | Non-Uniform Cache Architecture (NUCA) | en_US |
dc.subject | Last Level Cache (LLC) | en_US |
dc.subject | Multi-core Processors (CMP) | en_US |
dc.title | Selective Cache Line Replication Scheme in Shared Last Level Cache | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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