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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/9724
Title: Study of Various Factors Affecting Performance of Multi-Core Processors
Authors: Chaturvedi, Nitin
Keywords: EEE
Chip Multiprocessors (CMP)
Multiple-Chip Multiprocessor (M-CMP)
Tiled Architecture
Issue Date: Jul-2013
Publisher: IJDPS
Abstract: Advances in Integrated Circuit processing allow for more microprocessor design options. As Chip Multiprocessor system (CMP) become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single chip. This enables sharing of computation resources that was not previously possible. In addition the virtualization of these computation resources exposes the system to a mix of diverse and competing workloads. On chip Cache memory is a resource of primary concern as it can be dominant in controlling overall throughput. This Paper presents analysis of various parameters affecting the performance of Multi-core Architectures like varying the number of cores, changes L2 cache size, further we have varied directory size from 64 to 2048 entries on a 4 node, 8 node 16 node and 64 node Chip multiprocessor which in turn presents an open area of research on multicore processors with private/shared last level cache as the future trend seems to be towards tiled architecture executing multiple parallel applications with optimized silicon area utilization and excellent performance.
URI: 10.5121/ijdps.2013.4404
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9724
Appears in Collections:Department of Electrical and Electronics Engineering

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