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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/9728
Title: Design of a Low Power Approximate Adder based on Magnetic Tunnel Junction for Image Processing Applications
Authors: Chaturvedi, Nitin
Keywords: EEE
Power demand
PSNR
Nonvolatile memory
Very large scale integration (VLSI)
Approximation algorithms
Issue Date: 2021
Publisher: IEEE
Abstract: With the growth of big data applications such as voice/speech recognition, data mining, and computer vision, conventional computing system faces significant challenges. The increasing computational complexity and large data set results in large power consumption. To address this challenge, we propose to combine the benefits of approximate and in-memory computing which effectively reduces power consumption without any significant impact on the output. In this work, a low power approximate adder based on nonvolatile memory element (Magnetic Tunnel Junction (MTJ)) is designed for a wide range of applications. Furthermore, the proposed approximate adder is demonstrated to perform edge detection on a 512x512 image using the Sobel Edge Detection Algorithm. The effect on the quality of image using metrics like mean square error (MSE), peak signal to noise ratio (PSNR), and structural similarity index (SSIM) are also investigated.
URI: https://ieeexplore.ieee.org/document/9440080
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9728
Appears in Collections:Department of Electrical and Electronics Engineering

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