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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chaturvedi, Nitin | - |
dc.date.accessioned | 2023-03-15T05:35:17Z | - |
dc.date.available | 2023-03-15T05:35:17Z | - |
dc.date.issued | 2021 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/9440080 | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9728 | - |
dc.description.abstract | With the growth of big data applications such as voice/speech recognition, data mining, and computer vision, conventional computing system faces significant challenges. The increasing computational complexity and large data set results in large power consumption. To address this challenge, we propose to combine the benefits of approximate and in-memory computing which effectively reduces power consumption without any significant impact on the output. In this work, a low power approximate adder based on nonvolatile memory element (Magnetic Tunnel Junction (MTJ)) is designed for a wide range of applications. Furthermore, the proposed approximate adder is demonstrated to perform edge detection on a 512x512 image using the Sobel Edge Detection Algorithm. The effect on the quality of image using metrics like mean square error (MSE), peak signal to noise ratio (PSNR), and structural similarity index (SSIM) are also investigated. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | EEE | en_US |
dc.subject | Power demand | en_US |
dc.subject | PSNR | en_US |
dc.subject | Nonvolatile memory | en_US |
dc.subject | Very large scale integration (VLSI) | en_US |
dc.subject | Approximation algorithms | en_US |
dc.title | Design of a Low Power Approximate Adder based on Magnetic Tunnel Junction for Image Processing Applications | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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