![DSpace logo](/jspui/image/logo.gif)
Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/9729
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chaturvedi, Nitin | - |
dc.date.accessioned | 2023-03-15T05:39:22Z | - |
dc.date.available | 2023-03-15T05:39:22Z | - |
dc.date.issued | 2021-05 | - |
dc.identifier.uri | https://link.springer.com/chapter/10.1007/978-981-16-0749-3_39 | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9729 | - |
dc.description.abstract | In this work, the simulation-based performance comparisons of the Si nanowire FET have been done for gate length scaling from 90 to 32 nm technology node. The study involves the design and optimization of the critical parameters for improved electrostatic control on the channel. The impact of gate length scaling on the off-state leakage current and threshold voltage roll-off concepts has been discussed. The study reports a drain current enhancement of 48.72 and 72.12% for gate length scaling from 90 to 45 nm and 90 nm to 32 nm technology node, respectively. The maximum mobility of the carrier up to 1173.86 cm−2/V. sand Ion/Ioff ratio of ~109 has been reported. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Springer | en_US |
dc.subject | EEE | en_US |
dc.subject | Nanowires | en_US |
dc.subject | Field-effect transistors (FETs) | en_US |
dc.subject | Electrostatic potential | en_US |
dc.subject | Quantum effects | en_US |
dc.title | Off-State Leakage Concern in Scaling Nanowire FETs | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.