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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/9730
Title: Performance Analysis of GaN and ZnO Gate All Around Nanowire FET at sub-5nm Technology
Authors: Chaturvedi, Nitin
Keywords: Nanowire
EEE
NEGF
Nanostructure
FET
Issue Date: 2020
Publisher: IEEE
Abstract: In this work, a simulation-based analysis and performance comparison of the Gate All Around Nanowire FET (GAA NW FET) has been carried out for Si, GaN, and ZnO-based GAA NW FET. The Ion/Ioff ratio was found to be 10 5 , 10 9 , and 10 8 for Si, GaN, and ZnO NW FET, respectively. A reduction of 47.42% for GaN NW FET and 6.53% for ZnO NW FET were observed against Si NW FET in the SS value. For DIBL analysis, a reduction of 23.75% for GaN NW FET and 1.67% for ZnO NW FET were observed against Si NW FET. The study concludes that integrated amalgamation of the excellent material properties of GaN with nanowire structure makes GaN NW FET an intriguing option for the next generation digital logic applications.
URI: https://ieeexplore.ieee.org/document/9776873
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9730
Appears in Collections:Department of Electrical and Electronics Engineering

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