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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/9737
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dc.contributor.authorChaturvedi, Nitin-
dc.date.accessioned2023-03-15T06:58:59Z-
dc.date.available2023-03-15T06:58:59Z-
dc.date.issued2017-
dc.identifier.urihttps://ieeexplore.ieee.org/abstract/document/8004051-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9737-
dc.description.abstractWith the advent of technology, a change from feature size to nanometer regime resulted in the scaling of operating voltages and dimensions. Reducing them can greatly boost the energy efficiency but it also leads to increased design challenges. To deal with the activity limitations imposed by the low overdrive voltage and the intrinsic read stability/write margin trade off, large scale SRAM arrays largely rely on assist techniques. These techniques address the problem of preserving the functionality of the 6T SRAM cell by improving the read and write margins of the cell. In this paper, we show a comprehensive analysis of the effectiveness of some assist methods. This paper presents the margin sensitivity analysis of assist techniques to assess the productiveness of assist methods and to investigate their direct impact on the voltage sensitive yield. In addition, the effect of temperature variation and process variation have also been analyzeden_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectAssist Techniquesen_US
dc.subjectRead noise marginen_US
dc.subjectSRAM Cellsen_US
dc.subjectStatic noise marginen_US
dc.subjectWrite noise marginen_US
dc.titleA comparative analysis of read/write assist techniques on performance & margin in 6T SRAM cell designen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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