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Title: | FPGA implementation of interpolation techniques for thermistor linearization |
Authors: | Mishra, Puneet |
Keywords: | EEE Thermistor Temperature measurement Field-programmable gate array (FPGA) Interpolation Linearization |
Issue Date: | 2015 |
Publisher: | IEEE |
Abstract: | Thermistor is a novel temperature sensing device as it is highly sensitive while being rugged, compact and of low cost. The only drawback with a thermistor is its exponential nonlinear relation between temperature and resistance. Therefore, a mechanism to make the thermistor a linear device is an essential requirement for thermistor based temperature measurements. Several linearizing techniques have been proposed by the researchers, and out of these, interpolation is widely used due to its easy implementation while offering good linearity. The present work aims to provide a comparative study for five interpolation based linearization methods namely Nearest, Linear, Spline, Cubic Hermite and Lagrange. These techniques have been successfully simulated and implemented on FPGA in LabVIEW environment and a performance comparison has been made on the basis of the Mean Square Error (MSE), Mean Absolute Deviation (MAD) and hardware resource (HR) utilization. In this paper, MSE for Nearest, Linear, Spline, Hermite and Lagrange has been found to be 247.5×10-6, 71.5×10-6, 7.57×10-6, 25.5×10-6 and 2.84×10-6 respectively and MAD has been found to be 52.6×10-4, 20.008×10-4, 7.07×10-4, 9.92×10-4 and 3.142×10-4 respectively for 20 sections. It was also observed that nearest interpolation used minimum (21% slices), Hermite used maximum (71% slices) and Lagrange method used moderate (42% slices) HR. Experimental validation results demonstrated MSE for Nearest, Linear, Spline, Hermite and Lagrange interpolation as 583.47×10-6, 146.2×10-6, 63.165×10-6, 77.97×10-6, and 6.86×10-6, respectively and MAD of 75.886×10-4, 44.128×10-4, 20.9×10-4, 22.635×10-4 and 9.1129×10-4, respectively. Based on the above result Lagrange method offers the best interpolation while utilizing HR. |
URI: | https://ieeexplore.ieee.org/abstract/document/7375044 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9886 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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