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Issue Date
Title
Author(s)
2020-07
Effect of Device Dimensions, Layout and Pre-Gate Carbon Implant on Hot Carrier Induced Degradation in HKMG nMOS Transistors
Rao, V. Ramgopal
2017-08
PBTI in HKMG nMOS Transistors— Effect of Width, Layout, and Other Technological Parameters
Rao, V. Ramgopal
2006-08
The Effects of Varying Tilt Angle of Halo Implant on the Performance of Sub 100nm LAC MOSFETs
Rao, V. Ramgopal
2003
Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs
Rao, V. Ramgopal
2003-02
A novel dynamic threshold operation using electrically induced junction MOSFET in the deep sub-micrometer CMOS regime
Rao, V. Ramgopal
2005
A new drain voltage enhanced NBTI degradation mechanism [pMOSFETs]
Rao, V. Ramgopal
2004-07
Sub-threshold Swing Degradation due to Localized Charge Storage in SONOS Memories
Rao, V. Ramgopal
2002-07
Physical mechanisms for pulsed AC stress degradation in thin gate oxide MOSFETs
Rao, V. Ramgopal
2001-10
Characterization of lateral asymmetric channel (LAC) thin film SOI MOSFETs
Rao, V. Ramgopal
1998-10
Sub-0.18 /spl mu/m SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology
Rao, V. Ramgopal
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Subject
2
Nonvolatile memory
2
Pulse measurements
2
Very large scale integration
1
Amorphous materials
1
Capacitance
1
Channel hot electron injection
1
Communication industry
1
Dipole
1
Electronic devices
1
Electronics industry
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