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Results 21-30 of 68 (Search time: 0.003 seconds).
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Item hits:
Issue Date
Title
Author(s)
2008-07
A novel sub-1 volt bandgap reference with all CMOS
Gupta, Anu
2013-12
A comparative analysis of power and delay optimise digital logic families for high performance system design
Gupta, Anu
2013
Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology
Gupta, Anu
2009-12
Design of a High Performance, Low Power, Fully Differential Telescopic Cascode Amplifier using Common-Mode Feedback Circuit
Gupta, Anu
2009
A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers
Gupta, Anu
2011
Novel Method To Implement High Frequency All Digital Phase-Locked Loop On FPGA
Gupta, Anu
2010
Hardware Implementation of a Biometric Fingerprint Identification System with Embedded Matlab
Gupta, Anu
;
Chaturvedi, Nitin
2013
Characterization of Logical Effort for Improved Delay
Gupta, Anu
2012
Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology
Gupta, Anu
2013
A high gain, high CMRR two-stage fully differential amplifier using gm/Id technique for bio-medical applications
Gupta, Anu
Discover
Author
19
Asati, Abhijit
3
Asati, Abhijit
3
Chaturvedi, Nitin
3
Gupta, Rajiv
3
Shekhar, Chandra
1
Shenoy, Meetha V.
Subject
4
Carbon nanotube field effect tran...
4
Iris localization
4
Logical effort
4
Power-delay product (PDP)
3
Architecture
3
Carbon nanotube (CNT) field effec...
3
Carry ripple adder(CRA)
3
CMOS technology
3
iris recognition
3
Iris segmentation
.
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Date issued
3
2020 - 2022
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2010 - 2019
12
2005 - 2009