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Issue Date
Title
Author(s)
2003
Device and circuit performance issues with deeply scaled high-K MOS transistors
Rao, V. Ramgopal
2004-06
Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations
Rao, V. Ramgopal
2003-04
Highly conducting doped poly-Si deposited by hot wire CVD and its applicability as gate material for CMOS devices
Rao, V. Ramgopal
2003-10
CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters
Rao, V. Ramgopal
2003-12
Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance
Rao, V. Ramgopal
2003-04
Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors
Rao, V. Ramgopal
2003-04
A new method to characterize border traps in submicron transistors using hysteresis in the drain current
Rao, V. Ramgopal
2003-08
Reliability of ultrathin JVD silicon nitride MNSFETs under high field stressing
Rao, V. Ramgopal
2001-09
Low temperature silicon nitride deposited by Cat-CVD for deep sub-micron metal–oxide–semiconductor devices
Rao, V. Ramgopal
2000-04
Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs
Rao, V. Ramgopal
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Subject
37
MOSFETs
9
Degradation
9
MOSFET circuits
7
Capacitance
7
CMOS technology
7
FinFETs
7
Threshold voltage
6
Circuit simulation
6
Hot carriers
6
Los Angeles Council
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2009
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