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Results 1-10 of 71 (Search time: 0.003 seconds).
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Issue Date
Title
Author(s)
2018-11
Constant power consumption design of novel differential logic gate for immunity against differential power analysis
Gupta, Anu
2015
Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis
Gupta, Anu
2015-04
Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology
Gupta, Anu
2013
CNTFET based design of content addressable memory cells
Gupta, Anu
2013-08
Design of CNTFET-based 2-bit ternary ALU for nanoelectronics
Gupta, Anu
2014
A Novel Design of Ternary Full Adder Using CNTFETs
Gupta, Anu
2014
An Operational Amplifier With Recycling Folded Cascode Topology And Adaptive Biaisng
Gupta, Anu
2013-02
A Novel Ultra Low Power, High Impedance Current Mirror Circuit for Biasing Operational Amplifier in Sub-threshold Region
Gupta, Anu
2012
Performance Evalution Of CNTFET-Based Sram Cell Design
Gupta, Anu
2012
Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology
Gupta, Anu
Discover
Author
19
Asati, Abhijit
4
Gupta, Rajiv
3
Asati, Abhijit
3
Chaturvedi, Nitin
3
Shekhar, Chandra
1
Shenoy, Meetha V.
Subject
68
EEE
4
Carbon nanotube field effect tran...
4
Iris localization
4
Logical effort
4
Power-delay product (PDP)
3
Architecture
3
Carbon nanotube (CNT) field effec...
3
Carry ripple adder(CRA)
3
CMOS technology
3
iris recognition
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