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Results 31-40 of 58 (Search time: 0.002 seconds).
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Issue Date
Title
Author(s)
2020-10
High-Level synthesis assisted design and verification framework for automotive radar processors
Asati, Abhijit
;
Shekhar, Chandra
2015
Design and ASIC implementation of column compression Wallace/Dadda multiplier in sub-threshold regime
Gupta, Anu
;
Asati, Abhijit
2008
A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic
Asati, Abhijit
;
Shekhar, Chandra
2013
Automated HDL Generation of Two’s Complement Wallace Multiplier With Paralle Prefix Adders
Asati, Abhijit
2016-02
A modular approach to random task graph generation
Asati, Abhijit
2020
Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes
Asati, Abhijit
2012
Hardware software co-design using profiling and clustering
Asati, Abhijit
2022-07
Dedicated hardware architecture for localizing iris in VW images
Asati, Abhijit
;
Gupta, Anu
2013
Automated HDL generation of two’s complement Dadda multiplier with Parallel Prefix Adders
Asati, Abhijit
2022-12
Analysis of Logical Effort-Based Optimization in the Deep Submicron Technologies
Asati, Abhijit
Discover
Author
19
Gupta, Anu
17
Shekhar, Chandra
1
Shenoy, Meetha V
1
Shenoy, Meetha V.
Subject
5
High-level synthesis (HLS)
4
Iris localization
3
Clock gating
3
Han-Carlson Adder
3
iris recognition
3
Iris segmentation
3
LTSpice
3
MATLAB HDL coder
3
Power-delay product (PDP)
3
Sub-threshold
.
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Date issued
19
2020 - 2022
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2010 - 2019
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2008 - 2009
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58
false