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Results 1-7 of 7 (Search time: 0.002 seconds).
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Item hits:
Issue Date
Title
Author(s)
2009
A high-speed, hierarchical 16×16 array of array multiplier design
Asati, Abhijit
;
Shekhar, Chandra
2009-08
A Novel Redundant Binary Number to Natural Binary Number Converter
Gupta, Anu
;
Shekhar, Chandra
;
Asati, Abhijit
2008
An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style
Asati, Abhijit
;
Shekhar, Chandra
2009-05
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Logic Design Style With Improved Performance
Asati, Abhijit
;
Shekhar, Chandra
2009-11
VLSI Implementation of a High Performance Barrel Shifter Architecture using Three Different Logic Design Styles
Asati, Abhijit
;
Shekhar, Chandra
2008
A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic
Asati, Abhijit
;
Shekhar, Chandra
2009
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load
Asati, Abhijit
;
Shekhar, Chandra
Discover
Author
1
Gupta, Anu
Subject
1
CMOS process
1
CMOS technology
1
Complexity theory
1
Delay
1
Digital circuit design
1
Digital signal processing
1
Inverters
1
Logic design
1
Logic design styles
1
Logic devices
.
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Date issued
5
2009
2
2008
Has File(s)
7
false