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Results 51-58 of 58 (Search time: 0.003 seconds).
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Item hits:
Issue Date
Title
Author(s)
2020
Area-optimal FPGA implementation of the YOLO v2 algorithm using High-Level Synthesis
Asati, Abhijit
;
Shekhar, Chandra
2016
Effectiveness of body bias & hybrid logic: An energy efficient approach to design adders in sub-threshold regime
Gupta, Anu
;
Asati, Abhijit
2009
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load
Asati, Abhijit
;
Shekhar, Chandra
2019-09
Low-voltage, low-power SRAM circuits using subthreshold design technique
Asati, Abhijit
;
Gupta, Anu
2012
Design of a Static Current Simulator Using Device Matrix Approach
Asati, Abhijit
2018
Optimizing the Ratio of Number of Tubes in PCNTFET to NCNTFET for Digital Circuits
Asati, Abhijit
2022-05
Computational Operations and Hardware Resource Estimation in a Convolutional Neural Network Architecture
Asati, Abhijit
;
Shenoy, Meetha V
2021-11
A Novel Method for Suitable Hyperparameter Selection in an Accurate Convolutional Neural Network Architecture
Asati, Abhijit
;
Shenoy, Meetha V.
Discover
Author
19
Gupta, Anu
17
Shekhar, Chandra
1
Shenoy, Meetha V
1
Shenoy, Meetha V.
Subject
5
High-level synthesis (HLS)
4
Iris localization
3
Clock gating
3
Han-Carlson Adder
3
iris recognition
3
Iris segmentation
3
LTSpice
3
MATLAB HDL coder
3
Power-delay product (PDP)
3
Sub-threshold
.
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Date issued
19
2020 - 2022
31
2010 - 2019
8
2008 - 2009
Has File(s)
58
false