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Results 21-30 of 40 (Search time: 0.003 seconds).
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Item hits:
Issue Date
Title
Author(s)
2015
Selective Cache Line Replication Scheme in Shared Last Level Cache
Chaturvedi, Nitin
2021-05
Off-State Leakage Concern in Scaling Nanowire FETs
Chaturvedi, Nitin
2019
Design of a Robust Logic Gate using Magnetic Tunnel Junction
Chaturvedi, Nitin
2020
Design of a Low Power 11T-1MTJ Non-Volatile SRAM Cell with Half-Select Free Operation
Chaturvedi, Nitin
2017
An exploration of neuromorphic systems and related design issues/challenges in dark silicon era
Chaturvedi, Nitin
2020
Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array
Chaturvedi, Nitin
2017
A comparative analysis of read/write assist techniques on performance & margin in 6T SRAM cell design
Chaturvedi, Nitin
2017
Design and analysis of 6T SRAM cell with NBL write assist technique using FinFET
Chaturvedi, Nitin
2018
Multiple Solutions for Reconfiguration to Address Partial Shading Losses in Solar Photovoltaic Arrays
Chaturvedi, Nitin
2019
A Novel Low Power Non-Volatile SRAM Cell with Self Write Termination
Chaturvedi, Nitin
Discover
Author
3
Gupta, Anu
1
Asati, Abhijit
1
Chowdhury, Rajdeep
1
Gupta, Navneet
1
Pande, Surojit
1
Shenoy, Meetha V.
Subject
4
Chip Multiprocessors (CMP)
4
Last Level Cache (LLC)
4
Multi-core Processors (CMP)
4
Non-Uniform Cache Architecture (N...
4
Spin Transfer Torque-Magnetic Tun...
2
Amplifiers
2
Cascade
2
In-Memory Computing (IMC)
2
Low Power
2
Magnetic Random-Access Memory (MRAM)
.
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Date issued
15
2020 - 2022
24
2010 - 2019
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2009 - 2009