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Issue Date
Title
Author(s)
2013
Characterization of Logical Effort for Improved Delay
Gupta, Anu
2016
Effectiveness of body bias & hybrid logic: An energy efficient approach to design adders in sub-threshold regime
Gupta, Anu
;
Asati, Abhijit
2019-02
Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology
Vidhyadharan, Sanjay
2019-02
Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology
Vidhyadharan, Sanjay
2010
Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework
Rao, V. Ramgopal
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Author
2
Gupta, Anu
2
Vidhyadharan, Sanjay
1
Asati, Abhijit
1
Rao, V. Ramgopal
Subject
1
Logical effort
1
Operational amplifiers
1
Performance evaluation
1
Skewed gate
1
Sub-threshold Regime
1
Tunnel FET Device Structure
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