This paper proposes a novel geometric programming based formulation to solve a gate-sizing and retiming problem in the context of circuit optimization. The gate-sizing aspect of the problem involves continuous variables ...

This paper presents a pair of novel techniques to speed-up path-based Monte-Carlo simulation for statistical timing analysis of digital integrated circuits with no loss of accuracy. The presented techniques can be used in ...

The problem of yield estimation and optimization of analog circuits is addressed in this paper. Given convex design-space constraints that define the feasible region for the design, we first linearize the feasible region ...