Browsing by Author "Vidhyadharan, Sanjay"

An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications

Vidhyadharan, Sanjay (Springer, 2019-11)

Adiabatic circuits are ideally suited for implementing RFID tags and biomedical sensors due to their ultra-low power requirements. This paper presents a novel Gate Overlap Tunnel FET (GOTFET) based Advanced Adiabatic Logic ...

Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology

Vidhyadharan, Sanjay (Springer, 2019-02)

This paper presents the circuit performance of an optimized TFET device whose performance is not only better than most of the TFET devices reported in current literature, but exceeds the performance of state-of-the-art ...

CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications

Vidhyadharan, Sanjay (Springer, 2021-09)

This paper presents Carbon Nanotube FET (CNFET) based ultra-low-power Schmitt trigger SRAM designs which can operate at voltage levels as low as 200 mV, with high Static Noise Margins (STM) of 100–120 mV. The hysteresis ...

CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder

Vidhyadharan, Sanjay (Springer, 2021-02)

This paper proposes a carbon nanotube FET (CNFET)-based ultra-low-power dual-VDD ternary half adder (HA) circuit. The proposed design utilizes both the available ternary power supply voltages (VDD & VDD/2) and prevents ...

An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices

Vidhyadharan, Sanjay (IEEE, 2019)

Recent studies have indicated that multilogic circuits in VLSI design helps in reducing the transistor count of circuits and increases the data transfer rate significantly. This paper presents an efficient design methodology ...

An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices

Vidhyadharan, Sanjay (IEEE, 2021-01)

This paper presents a novel ultra-low power yet high-performance device and circuit design paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs (GOTFETs) and Carbon Nanotube FETs (CNFETs). ...

Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator

Vidhyadharan, Sanjay (Taylor & Francis, 2023-01)

This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less ...

Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications

Vidhyadharan, Sanjay (CRC, 2021)

The advancement in complementary metal oxide semiconductor (CMOS) technology during the last few decades has enabled scaling down of the metal oxide semiconductor field-effect transistor (MOSFET) feature size to below the ...

Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

Vidhyadharan, Sanjay (Emerald, 2021-03)

Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a ...

Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node

Vidhyadharan, Sanjay (Springer, 2020-01)

In this paper, four different types of gate-overlap tunnel FET (GOTFET) devices are proposed for ultra-low power applications: (1) generic GOTFETs for digital logic, (2) low- and high-threshold (LVT and HVT) GOTFETs for ...

An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger

Vidhyadharan, Sanjay (Elsevier, 2020-10)

This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current Ion, while the off current Ioff remains around an order lower, than ...

Memristor–CMOS hybrid ultra-low-power high-speed multivibrators

Vidhyadharan, Sanjay (Springer, 2021-05)

Memristor–CMOS (MCM) technology enables fabrication of thin film memristors over the conventional CMOS devices and has the potential to significantly reduce the silicon-area and propagation delays in VLSI chips. The memristor ...

Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs

Vidhyadharan, Sanjay (Taylor & Francis, 2021-04)

This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser power and can be implemented ...

A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications

Vidhyadharan, Sanjay (Springer, 2019-06)

This paper introduces an innovative Gate Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield double the on current Ion, while the off current Ioff remains an order lower than the analogous ...

Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC

Vidhyadharan, Sanjay (Elsevier, 2020-07)

This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents Ion more than double, while ...

Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications

Vidhyadharan, Sanjay (IEEE, 2019)

For the first time, innovative low (LVT) and high (HVT) threshold tunnel FET devices have been reported for ternary logic applications. Based on an iterative algorithm, the DG TFET structures have been optimized such that ...

A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM

Vidhyadharan, Sanjay (Elsevier, 2021-05)

This paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as compared to the other CNTFET ternary SRAM designs reported in ...

A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder

Vidhyadharan, Sanjay (Taylor & Francis, 2020-03)

Recent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit double the on-currentsIon and one-tenth the off-currents Ioff than the equally sized MOSFETs at the same technology node, making them ...

Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology

Vidhyadharan, Sanjay (Springer, 2019-02)

In this work, the structure of a TFET device has been engineered such that it is not only better than most of the TFETs reported in literature, it’s performance is even better than the MOSFETs of the standard 45 nm CMOS ...

Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices

Vidhyadharan, Sanjay (Springer, 2020-07)

This paper investigates a method to suppress the ambipolar current Iamb effectively, enhance the device performance with higher on current Ion, lower off current Ioff, lower inverse subthreshold slope SS and simultaneously ...

Browsing by Author "Vidhyadharan, Sanjay"

Browsing by Author "Vidhyadharan, Sanjay"

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