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Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies
Rao, V. Ramgopal
(
IEEE
,
2006
)
Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K Gate Dielectrics
Rao, V. Ramgopal
(
IEEE
,
2001
)
Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETs
Rao, V. Ramgopal
(
IEEE
,
1997-12
)
Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique
Rao, V. Ramgopal
(
IEEE
,
2001-07
)
Energy Efficient Lif Neuron Circuit Using Hybrid Cmos-Nems in 65 Nm Cmos Technology
Rao, V. Ramgopal
(
IEEE
,
2022-01
)
Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework
Rao, V. Ramgopal
(
IEEE
,
2010
)
Filament study of STI type drain extended NMOS device using transient interferometric mapping
Rao, V. Ramgopal
(
IEEE
,
2009-12
)
Suppression of boron penetration by hot wire CVD polysilicon
Rao, V. Ramgopal
(
IEEE
,
2002
)
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Author
Rao, V. Ramgopal (10)
Vidhyadharan, Sanjay (4)
Gupta, Anu (3)
Asati, Abhijit (2)
Shekhar, Chandra (1)
Subject
CMOS technology (18)
EEE (18)
Circuit simulation (3)
45 nm CMOS technology (2)
Analog circuits (2)
Capacitance (2)
Circuit optimization (2)
CMOS process (2)
MOS devices (2)
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2020 - 2022 (3)
2010 - 2019 (5)
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