DSpace Repository
Search
Login
DSpace Home
→
Search
JavaScript is disabled for your browser. Some features of this site may not work without it.
Search
Search:
All of DSpace
BITS Audio/Video Collection
BITS Faculty Publications
BITS Library Events
BITS Photos & Memories
BITS Pilani, Dubai Campus
BITS Pilani Gallery
BITS Pilani, Goa Campus
BITS Pilani, Hyderabad Campus
BITS Publications
BITS Rare / Digitized Books
BITS Theses
Daily News
Placement & Career Development Service
Reference Tools & Materials
Filters
Use filters to refine the search results.
Current Filters:
Title
Author
Subject
Date issued
Has File(s)
Filename
File description
Contains
Equals
ID
Not Contains
Not Equals
Not ID
Title
Author
Subject
Date issued
Has File(s)
Filename
File description
Contains
Equals
ID
Not Contains
Not Equals
Not ID
New Filters:
Title
Author
Subject
Date issued
Has File(s)
Filename
File description
Contains
Equals
ID
Not Contains
Not Equals
Not ID
Showing 10 out of a total of 68 results.
(0.009 seconds)
Now showing items 1-10 of 68
1
2
3
4
. . .
7
Next Page
Sort Options:
Relevance
Title Asc
Title Desc
Issue Date Asc
Issue Date Desc
Results Per Page:
5
10
20
40
60
80
100
Constant power consumption design of novel differential logic gate for immunity against differential power analysis
Gupta, Anu
(
IET
,
2018-11
)
Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis
Gupta, Anu
(
Elsevier
,
2015
)
Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology
Gupta, Anu
(
Taylor & Francis
,
2015-04
)
CNTFET based design of content addressable memory cells
Gupta, Anu
(
IEEE
,
2013
)
Design of CNTFET-based 2-bit ternary ALU for nanoelectronics
Gupta, Anu
(
Taylor & Francis
,
2013-08
)
A Novel Design of Ternary Full Adder Using CNTFETs
Gupta, Anu
(
Springer
,
2014
)
An Operational Amplifier With Recycling Folded Cascode Topology And Adaptive Biaisng
Gupta, Anu
(
VLSICS
,
2014
)
A Novel Ultra Low Power, High Impedance Current Mirror Circuit for Biasing Operational Amplifier in Sub-threshold Region
Gupta, Anu
(
IJNIET
,
2013-02
)
Performance Evalution Of CNTFET-Based Sram Cell Design
Gupta, Anu
(
Inter Science
,
2012
)
Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology
Gupta, Anu
(
IJAEE
,
2012
)
Now showing items 1-10 of 68
1
2
3
4
. . .
7
Next Page
Sort Options:
Relevance
Title Asc
Title Desc
Issue Date Asc
Issue Date Desc
Results Per Page:
5
10
20
40
60
80
100
Browse
All of DSpace
Communities & Collections
By Issue Date
Authors
Titles
Subjects
My Account
Login
Register
Discover
Author
Gupta, Anu (68)
Asati, Abhijit (19)
Asati, Abhijit (3)
Chaturvedi, Nitin (3)
Gupta, Rajiv (3)
Shekhar, Chandra (3)
Shenoy, Meetha V. (1)
Subject
EEE (68)
Carbon nanotube field effect transistor (CNTFET) (4)
Iris localization (4)
Logical effort (4)
Power-delay product (PDP) (4)
Architecture (3)
Carbon nanotube (CNT) field effect transistor (CNTFET) (3)
Carry ripple adder(CRA) (3)
CMOS technology (3)
iris recognition (3)
... View More
Date Issued
2020 - 2022 (3)
2010 - 2019 (53)
2005 - 2009 (12)
Has File(s)
No (68)