Abstract:
The advancement in complementary metal oxide semiconductor (CMOS) technology during the last few decades has enabled scaling down of the metal oxide semiconductor field-effect transistor (MOSFET) feature size to below the 100 nano meter (nm) range. The power supply voltage across the devices must be reduced proportionately with the reduction in feature size to maintain the electric fields inside the device within junction breakdown limits. The gate overlaps the source completely, while it is terminated 22 nm short of the channel-drain junction. The gate overlaps the source completely, while it is terminated 22 nm short of the channel-drain junction. Jitter is the variation of the clock edge from its ideal instance. Clock jitter is usually caused by the clock generating circuit, noise, power supply fluctuations, and interference from adjacent components.