dc.contributor.author |
Rao, V. Ramgopal |
|
dc.date.accessioned |
2023-10-20T09:18:33Z |
|
dc.date.available |
2023-10-20T09:18:33Z |
|
dc.date.issued |
2021-02 |
|
dc.identifier.uri |
https://ieeexplore.ieee.org/document/9296248 |
|
dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12555 |
|
dc.description.abstract |
In this article, we demonstrate a double-clamped nano-electromechanical switch (NEMS) with low stand-by power as an effective solution to the leakage issues in scaled CMOS-based power gating (PG) in logic circuits. The proposed NEMS structure is achieved to have a low pull-in (~1.2 V), low hysteresis (<0.3 V), low turn-on delay (35 ns), and subthreshold slope of <6 mV/decade. This enables reduction in stand-by power dissipation in sub 10-nm CMOS technologies with a narrow 100 nm dimple gap for the low-power NEMS. We illustrate that the PG in ISCAS’85 benchmark circuits using the proposed fabricated NEMS shows significant leakage energy reduction for TON/TOFF<0.01 as compared to the sub 10-nm CMOS based PG. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
IEEE |
en_US |
dc.subject |
EEE |
en_US |
dc.subject |
FinFET |
en_US |
dc.subject |
ISCAS’85 |
en_US |
dc.subject |
Nano-electro mechanical switch (NEMS) |
en_US |
dc.subject |
Nanowire FET (NWFET) |
en_US |
dc.title |
Stand-by Power Reduction Using Experimentally Demonstrated Nano-Electromechanical Switch in CMOS Technologies |
en_US |
dc.type |
Article |
en_US |