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Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device

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dc.contributor.author Rao, V. Ramgopal
dc.date.accessioned 2023-10-25T04:22:28Z
dc.date.available 2023-10-25T04:22:28Z
dc.date.issued 2015-12
dc.identifier.uri https://ieeexplore.ieee.org/document/7307156
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12607
dc.description.abstract Shallow-trench isolation drain extended pMOS (STI-DePMOS) devices show a distinct two-stage breakdown. The impact of p-well and deep-n-well doping profile on breakdown characteristics is investigated based on TCAD simulations. Design guidelines for p-well and deep-n-well doping profile are developed to shift the onset of the first-stage breakdown to a higher drain voltage and to avoid vertical punch-through leading to early breakdown. An optimal ratio between the OFF-state breakdown voltage and the ON-state resistance could be obtained. Furthermore, the impact of p-well/deep-n-well doping profile on the figure of merits of analog and digital performance is studied. This paper aids in the design of STI drain extended MOSFET devices for widest safe operating area and optimal mixed-signal performance in advanced system-on-chip input-output process technologies. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject DePMOS Device en_US
dc.subject Avalanche breakdown en_US
dc.subject Drain extended MOSFET (DeMOS) en_US
dc.subject Input-output (I/O) en_US
dc.subject Mixed-signal perfor- mance en_US
dc.subject Well doping profile en_US
dc.title Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device en_US
dc.type Article en_US


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